The technology of fabricating semiconductor integrated circuits continues to advance in the number of transistors, capacitors, or other electronic devices which can be fabricated on a single integrated circuit chip. This increasing level of integration is being accomplished in large part by decreasing the minimum feature sizes. Even as the number of layers in the integrated circuit continues to increase, advanced processes are being used which allow for a reduction in the number of processing steps for a functional layer. However, these advanced processes often make extraordinary demands upon the chemistry of the etching process. Dielectric etching has presented some of the most difficult demands.
In the past the common materials for inter-level dielectric have been based upon silicon, such as silicon dioxide, silica glass such as BPSG, and related silicon-based oxide materials that serve as electrical insulators. Recently, interest has developed in insulating materials with low dielectric constants (low-k dielectrics), some of which are based upon silicon but others are based upon carbon.
Advanced integrated circuits contain multiple wiring layers separated from the silicon substrate and from each other by respective dielectric layers. Particularly logic circuitry, such as microprocessors, require several layers of metallization with intervening inter-level dielectric layers. Small contact or via holes need to be etched through each of the dielectric layers. The contact or via holes are then filled with a conductor, composed typically of aluminum in the past but more recently composed of copper. A horizontal wiring layer is formed over one dielectric layer and then covered by another dielectric layer. The horizontal wiring and the underlying vias are often referred to as a single wiring layer. The conventional process not only fills the contact or via holes but also overfills them to form a thick planar layer over both the filled holes and the dielectric. Conventionally, a metal lithographic step then photographically defines a photoresist layer over the planar metal layer and etches the exposed metal into a network of conductive interconnects.
In contrast, a recently developed damascene process substitutes chemical mechanical polishing for metal etching. A dual-damascene structure, as illustrated in sectioned isometric view in FIG. 1, has been proposed for advanced chips which avoids the metal etching and combines the metallization of the via and horizontal interconnect. There are two general types of dual-damascene processes, self-aligned and counterbore. The more conventional self-aligned dual-damascene process will be described first.
Over a substrate 10 is formed a thin lower stop layer 12 having a minimal thick of, for example 100 nm, a lower dielectric layer 14, having a thickness of, for example, 1 .mu.m or somewhat less, and a thin upper stop layer 16. The stop layers 12, 16 have compositions relative to the dielectric material such that a carefully chosen etch process that is selective to the material of the stop layer etches through the overlying dielectric but stops on the stop layer. Although copper metallization and low-k dielectric would more fully utilize the advantage of the dual-damascene structure, the present description will use silicon dioxide as the principal inter-level dielectric. Silicon dioxide is preferably grown by plasma-enhanced chemical vapor deposition (PECVD) using tetraethylorthosilicate (TEOS) as the main precursor gas. Silicon nitride (Si.sub.3 N.sub.4) is a common material for stop layers when the dielectric is an oxide. Silicon nitride is preferably also grown by PECVD to reduce the thermal budget, and its general composition is given by SiN.sub.x, where x may vary somewhat over a range of, for example 1 to 1.5. A dielectric photolithographic step is then performed to create circular holes 18 in the upper stop layer 16. The diameters of the circular holes 18 determine the diameters of the via holes, which usually represent the smallest dimension defined in the dielectric etch. The smallest defined lateral dimension in a level is often referred to as the critical dimension (CD). The dual-damascene structure can be used both at the power level, which is the uppermost metal layer, and at the signal levels, for example, metal-1 and metal-2 levels for a moderately complex logic chip. The power level typically has a larger via size, for example, 0.6 .mu.m, while the signal levels typically have smaller via sizes, for example, 0.3 .mu.m. This diameter is being reduced to 0.25 .mu.m and to yet lower sizes in advanced structures. Total dielectric thickness also varies between the power and signal levels. The etching in this photolithographic step is preferably selective to the principal dielectric material so that at this point the holes 18 do not significantly extend into the lower dielectric layer 14.
Then, in the continuation of the self-aligned dual-damascene process, an upper dielectric layer 20 is deposited to a thickness of, for example, 1.4 .mu.m over the partially etched structure, including deposition into the etched depressions in the patterned nitride layer 16. A photoresist mask is deposited and defined into the shape of a trench 22 having a width of, for example, 1.2 .mu.m and a much longer length. A self-aligned dual-damascene dielectric etch is then performed both to form the trench 22 in the upper oxide layer 20 and to extend the lower via holes 18 through the lower oxide layer 14 and down to the lower stop layer 12. The upper nitride stop layer 16 serves both as a stop for forming the trench 22 and as a hard mask for etching the via hole 18. The combined etch must not significantly etch the upper stop layer 16 at the floor 24 of the trench 22, and it must stop at the lower stop layer 12 at the bottom 26 of the via holes 18. In a further step, not illustrated here because it is generally considered to be non-crucial, a further non-selective etch removes the portion of the lower stop layer 12 at the bottom of the via hole 18 so as to expose the substrate 10 to contacting when metal is filled into the trench 22 and via hole 18.
In the self-aligned dual-damascene etch process, the selectivity of the oxide etch to nitride or other stop material in both the relatively open trench floor 24 and particularly at the shoulders 28 of the via holes 18 is especially crucial since these areas are exposed to the etching plasma while the via holes 18 are being etched. Generally, the shoulders 28 etch faster than the trench floor 24 because of the exposed geometry. The upper nitride layer 16 and its shoulder 28 are further exposed during a long over-etch of the lower oxide layer 14, typically greater than 100% to reliably open the via in the presence of process and other non-uniformities. Such selectivity can be achieved by use of a highly polymerizing chemistry which deposits a protective polymeric coating on the non-oxide surfaces and vertical oxide surfaces but generally not on the horizontal oxide surfaces. However, the extensive polymerization impacts the etching of the narrow and deep via holes 18 and may cause etch stop. Etch stop occurs when the side walls are so heavily polymerized that the polymer closes the hole and prevents further etching of the bottom of the hole. Of course, etch stop in the via holes 18 must be avoided. As a result, the process window for the self-aligned process is often limited by the conflicting requirements of the oxide etch to maintain the nitride shoulders 28 while continuing to open the oxide in the via hole 18. The etch must maintain the bottom critical dimension (CD) associated with the via hole 18 in order to maintain tight control of the via resistance. The top critical dimension associated with the trench 22 is less critical, but depending upon the pitch of via holes 18, it may determine the margin for shorting between vias associated with different trenches. The trench profile needs to be vertical to maintain consistent line widths.
Following the etching of the dual-damascene structure by either the self-aligned or counterbore process, a single metallization operation fills both the via holes 18 and the trench 22. The metallization operation may require that the trench 22 and via hole 18 be coated with barrier layers and wetting layers, as has become well known in metallization of small features in advanced integrated circuits. The metal deposition, usually performed at least partially by physical vapor deposition, is continued to the extent that the metal completely fills the via holes 18 and trench 22 and somewhat overlies the top 30 of the upper oxide layer 20. Chemical mechanical polishing is then performed, and because silica is much harder than metal the polishing stops when it encounters the upper oxide layer 20. Thereby, the metallization is restricted on the top of the wafer to the trench 22. The metallization may either serve both as a horizontal interconnect between two or more locations in the substrate through the via holes 18 and as an inter-level vertical interconnect in the via holes 18. The dual-damascene process is particularly useful for copper metallization because no copper etching is required.
In the self-aligned dual-damascene process, the lower stop layer 12 is photolithographically patterned before the upper dielectric layer 20 is deposited, and the trench and the via are etched in a single process step. Such a process requires balancing nitride selectivity against etch stop margin, and achieving a wide process window for an acceptable process poses a great challenge in developing an oxide etch recipe.
An alternative dual-damascene process, referred to as a counterbore dual-damascene process for reasons which will become apparent, separates the via and trench etch steps. Thereby, the nitride shoulder need not be exposed for such long times to the oxide etch so that the balance between selectivity and etch stop is eased. The counterbore process is thus advantageous for smaller via sizes.
The counterbore process is illustrated in the flow diagram of FIG. 2 with reference to the cross-sectional structures of FIGS. 3-8, which show the sequential development of the dual-damascene structure. In step 40, an unpatterned, planar dual-damascene structure is grown comprising, as illustrated in the cross-sectional view of FIG. 3, the substrate 10, the lower stop layer 12, the lower dielectric layer 14, the upper stop layer 16, and the upper dielectric layer 20. No photolithography is performed between the layers 12, 14, 16, and 20, and their compositions may be such to allow their growth by chemical vapor deposition (CVD) in a single plasma reaction chamber by varying the composition of the feed gas and the operating conditions between the layers.
In step 42, a first photoresist layer 44 is deposited and photographically patterned to form mask apertures 46 corresponding to the via or contact holes, only one of which is illustrated. It will be assumed that the underlying substrate 10 includes a metal surface in the area of the hole so it is properly called a via hole. Although the metal is preferably copper, the examples of the invention use an aluminum metallization. The composition of the metallization has very little effect upon the dielectric etch.
In a first etch step 48, an extended via hole 50, as illustrated in FIG. 4, is etched through the upper dielectric layer 20, the upper stop layer 16, and the lower dielectric layer 14 down to the lower stop layer 12. The etch chemistry is chosen to be selective to the material of the lower stop layer 12 so that the etch stops at the top surface 52 of the bottom stop layer 12.
In an unillustrated step, the first photoresist layer 44 is stripped. In step 54, a second photoresist layer 56, as illustrated in FIG. 5, is deposited and photographically patterned to form a mask aperture 58 corresponding to the trench. In a second etch step 60, a trench 62, illustrated in FIG. 6, is etched through the upper dielectric layer 20 down to the top surface 64 of the upper stop layer 16 without significantly eroding the top surface 52 of the bottom stop layer 12. The depth of the extended via hole 50 is thereby reduced to form a via hole 50'.
In a third etch step 66, the exposed portion of lower stop layer 12 at the bottom of the via hole 50' is etched, as illustrated in FIG. 7, through the lower stop layer 12 and down to an upper surface 68 of the substrate 10, which is typically a metal for a via. Depending upon the compositions of the two stop layers 12, 16, the third etch step 66 may remove portions of the upper stop layer 16 exposed at the bottom of the trench 62 to form a shelf 70 in the upper oxide layer 14, but this thin portion is not critical. In another unillustrated step, performed either before or after the third etch step 66, the second photoresist layer 56 is stripped along with any sidewall polymer forming in the dielectric etch.
Thereafter, as illustrated in FIG. 8, a metal 72 is filled into the trench 62 and underlying via hole 50' to contact the upper surface 68 of the substrate 10. Subsequent chemical mechanical polishing (CMP) removes any metal overflowing the trench 62. The metal 72 forms both a horizontal interconnect 74 and a via 76 contacting the underlying layer 10. As mentioned before, the metal 72 may be the conventional aluminum or the more advanced copper.
However, the counterbore etch process is very demanding. The first, via etch 48 of the extended via hole 50 is deep and narrow, the width usually representing the critical dimension of the process. The via etch 48 must etch through the upper stop layer 16 but stop on the lower stop layer 12. The deep via etch 48 thus requires a vertical profile and high selectivity to the bottom stop layer 12. Not only must the interconnect (trench) etch 60 stop on the upper stop layer 16, it must not significantly etch the lower stop layer 12, which is exposed during the entire interconnect etch. The interconnect etch 60 thus requires a vertical profile and high selectivity to the upper stop layer 16. If the lower stop layer 12 is inadvertently etched through during the long over-etch, an effect called punch through, the underlying metal is sputtered, and as a result device reliability is severely impacted, particularly if copper is used as the underlying metallization. All etch steps, but particularly those etching through the thicker dielectric layers, should be highly isotropic, producing nearly vertical side walls. To achieve the vertical profile, the etching of the stop layers should not significantly side etch the dielectric layers located above.
The first, via etch step 48 must selectively etch the upper stop layer 16 relative to the lower stop layer 12. This can be accomplished in a single etch step with the choice of significantly different materials for the two stop layer 12, 16. However, the choice is limited and not attractive. The growth of the planar structure of FIG. 3 is preferably performed in a single CVD reactor, which may be difficult to accomplish for materials of vastly different chemistries. Also, it is desired to form both stop layers 12, 16 out of materials having fairly good insulating properties. Use of conductive metals for either stop layer would form a grounding plane, thus introducing electrical coupling between interconnects on the same level. For similar reasons, the vertical extent of the stop layers formed of only fair insulators should be kept thin so as to reduce the lateral electrical conductance. Silicon nitride and related compounds such as some low-k silicon-based dielectrics have reasonably high resistivities, can be grown in the same chamber as oxides, and nitride-selective oxide etches are known, but it is not seen how to form two layers of such materials with vastly different etching characteristics while simultaneously maintaining high dielectric-to-stopper selectivity.
It is thus desired to find a etching process satisfying these difficult and conflicting requirements without unduly complicating and lengthening the dielectric etch step.